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SY89537L
3.3V Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer
General Description
The SY89537L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for enterprise switch, router, and multiprocessor server applications. This family is ideal for generating internal system timing requirements up to 700MHz for multiple ASICs, FPGAs, and NPUs. These devices integrate the following blocks into a single monolithic IC: * * * * * PLL (Phase-Lock-Loop) based synthesizer Fanout buffers Clock generator (dividers) Logic translation (LVPECL, LVDS)
Precision Edge(R)
Features
* Integrated programmable synthesizer with multiple output dividers, fanout buffers, and clock drivers * Direct interface to crystal: 14MHz to 18MHz * Input MUX accepts a reference and a crystal (XTAL) source - Ideal for reference backup clock source or system test frequency source - Patent-pending unique input MUX isolates XTAL and reference inputs minimizes crosstalk * Guaranteed AC performance: - 87.15MHz to 700MHz output frequency range (with RFCK at 16.6MHz) - <100psPP total jitter - <7psRMS cycle-to-cycle jitter - <8psPP deterministic jitter - <0.7psRMS crosstalk induced jitter - <50ps bank-to-bank skew * Output bank synchronization control pin * LVPECL and LVDS outputs * TTL/CMOS compatible control logic * Five independently programmable output frequency banks: - Four differential LVPECL output banks - One differential LVDS output bank with 3 output pairs * Separate output enable for each bank * 3.3V 10% power supply (2.5V output capable) * Guaranteed over the commercial and industrial temperature range (-40C to +85C) * Available in 44-pin (7mm x 7mm) MLFTM package
Five independently programmable output banks This level of integration minimizes additive jitter and part-to-part skew associated with discrete alternatives, resulting in superior system-level timing with reduced board space and power. For applications that require a zero-delay function, see the SY89538L. All support documentation can be found on Micrel's web site at: www.micrel.com.
Applications
* Enterprise routers, switches, servers and workstations * Parallel processor-based systems * Internal system clock generation for ASICs, NPUs, FPGAs
Markets
* LAN/WAN * Enterprise servers * Test and measurement
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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SY89537L
Functional Block Diagram
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Ordering Information(1)
Part Number SY89537LMG SY89537LMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-44 MLF-44
Operating Range Industrial Industrial
Package Marking SY89537LMG with Pb-Free bar-line indicator SY89537LMG with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
44-Pin MLFTM (MLF-44)
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Pin Description
Power
Pin Number 1 Pin Name VCCA VCCD Pin Function Analog PLL Power Pin: Connects to "quiet" 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. Bypass with 0.1F//0.01F low ESR capacitors and place as close to the VCCA pin as possible. Digital Logic Core Power Pin: VCCD connects to a 3.3V supply. Power pins are not internally connected on the die, and must be connected together on the PCB. Bypass with 0.1F//0.01F low ESR capacitors and place bypass capacitors as close to the VCCD pin as possible. LVDS and LVPECL Output Driver Power Pins: The outputs can be powered from a 2.5V supply or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V 10% or 2.5V 5%. Power pins are not internally connected on the die, and must be connected together on the PCB. Bypass with 0.1F//0.01F low ESR capacitor and place as close to the VCCO pin as possible. PLL Ground: Connect to "quiet" ground. GNDA and GND are not internally connected on the die, and must be connected on the PCB. Ground: GND pins and exposed pad must both be connected to the most negative potential of the chip ground.
3
14, 27, 30, 36
VCCO
10 11, 21, 22
GNDA GND, Exposed Pad
Control and Configuration
Pin Number 43 44 2, 4 Pin Name LR LF RSEL1, RSEL0 Pin Function Analog Input/Output: Provides the reference voltage for the PLL loop filter and is used with the LF pin. See "External Loop Filter Considerations" for recommended loop filter values. Analog Input/Output: Provides the loop filter node for the PLL. See "External Loop Filter Considerations" for loop filter values. TTL/CMOS Reference Input Pre-scaler. The two-bit input pre-scaler divides the input reference frequency by /1, /2, /4, or /8. RSEL0 is the LSB bit. See "Reference Input Divider Select Table," for proper decoding. The threshold voltage VTH = VCC/2. Internal 25k pull-up. TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input. Internal 25k pull-up. The default is logic HIGH, and selects the XTAL input. The threshold voltage VTH = VCC/2. Logic HIGH: XTAL Select Logic LOW: Reference Input Select TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL and LEN are used to decode the selection and the post divider of the LVDS output bank. LSEL includes an internal 25k pull-up. See "LVDS Output and Frequency Select Table" for proper decoding. The threshold voltage VTH = VCC/2. TTL/CMOS Input Enable Pin. Used to control the LOUT0-LOUT2 outputs and acts as a frequency select pin. LEN and LSEL are used to decode the selection and the post divider of the LVDS output bank. See the "LVDS Output and Frequency Select Table" for proper decoding. LEN includes an internal 25k pull-up. When disabled, LOUT0-LOUT2 outputs are LOW, and the complimentary outputs are HIGH. The threshold voltage VTH = VCC/2. TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx and PENx are used together to decode the selection and post divider of the PECL outputs. PSELx pins include an internal 25k pull-up. The threshold voltage VTH = VCC/2. See "PECL Output Frequency and Select Table" for proper decoding. TTL/CMOS input enable pin. Used to control the POUT0-PECL2 outputs and acts as a frequency select pins. PENx and PSELx are used together; see the "PECL Output and Frequency Select Table" for proper decoding. PENx includes an internal 25k pull-up. When disabled, PECL0-PECL2 outputs are LOW. The threshold voltage VTH = VCC/2. TTL/CMOS output bank synchronization control. Internal 25k pull-up. The default state is HIGH. After any bank has been programmed, all PECL and LVDS outputs are synchronized when the SYNC control pin is toggled with a HIGH-LOW-HIGH transition. See "Synchronization" section for details. The threshold voltage VTH = VCC/2.
7
INSEL
23
LSEL
24
LEN
17 19 39 41 18 20 40 42 33
PSEL0 PSEL1 PSEL2 PSEL3 PEN0 PEN1 PEN2 PEN3 SYNC
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Pin Description (continued)
Input/Output
Pin Number 5, 6 Pin Name RFCK, /RFCK XTAL2, XTAL1 Pin Function Reference Clock Differential Input. Input accepts any input, single-ended or differential: TTL/CMOS, LVPECL, LVDS, HSTL, and SSTL. RFCK requires external termination. See "Input Interface" section for details. Crystal Input. Directly connect a series resonant crystal across inputs. See "Quartz Crystal Oscillator Specification" table. Place crystal as close to the input as possible, keep XTAL and traces away from adjacent noisy traces to minimize noise coupling, and place the XTAL on the same side as the SY89537L (component side). 100K LVPECL Output Drivers. Terminate all PECL outputs with 50 to VCCO-2V. Each output pair has respective output frequency control (PSELx, PENx) pins. See "PECL Output and Frequency Select Table" for proper coding. For low jitter applications, unused PECL output pairs should be terminated with pull-down resistors. See "Output Termination Recommendations" section for termination detail. Differential LVDS Compatible Output Drivers. Output termination is 100 across the pair. For low-jitter applications, unused LVDS output pairs should be terminated with 100 across the pair. See "Output Termination Recommendations" section for details.
8, 9
12, 13 15, 16 34, 35 37, 38 25, 26 28, 29 31, 32
POUT0, /POUT0 POUT1, /POUT1 POUT2, /POUT2 POUT3, /POUT3 LOUT0, /LOUT0 LOUT1, /LOUT1 LOUT2, /LOUT2
Reference Input Driver Select Table
RSEL1 0 0 1 1 RSEL0 0 1 0 1 Internal Reference Clock RFCK / 8 RFCK / 4 RFCK / 2 RFCK / 1
Table 1. Reference Input Divider Select Table
Output and Frequency Select Tables
PSELx 0 0 1 1 PENx 0 1 0 1 POUTx Disable Output (VCO/4) / 2 (VCO/4) / 8 (VCO/4) / 1
Table 2. PECL Output and Frequency Select Table LSEL 0 0 1 1 LEN 0 1 0 1 LOUTx Disable Output (VCO/4) / 2 (VCO/4) / 8 (VCO/4) / 1
Table 3. LVDS Output and Frequency Select Table
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) .......................... -0.5V to +4.0V Input Voltage (VIN) .................................. -0.5V to VCC XTAL Input Voltage (VXTAL1, 2) ......... VCC -1.9V to VCC Output Current (IOUT) LVPECL Outputs ......................................50mA LVDS Outputs...........................................10mA Lead Temperature (soldering, 20 sec.) .......... +260C Storage Temperature (Ts) ................. -65C to 150C
Operating Ratings(2)
Supply Voltage (VCCD, VCCA) ...................... +3.0V to +3.6V Supply Voltage (VCCO)........................... +2.375V to +3.6V Ambient Temperature (TA)....................... -40C to +85C Package Thermal Resistance(3) MLFTM (JA) Still-Air.........................................................24C/W MLFTM (JB) Junction-to-Board..........................................8C/W
DC Electrical Characteristics(4)
Power Supply TA = -40C to +85C, unless otherwise stated.
Symbol VCCA VCCD VCCO ICC ICCA ICCO ICCD Parameter PLL Power Supply Control Logic Supply Voltage Output Supply Voltage Total Power Supply Current Analog Supply Current Output Supply Current Digital Supply Current No load, max. VCC, Note 6 Max. VCC No load, max. VCC Max. VCC Condition Note 5 Note 5 Min 3.0 3.0 2.375 3.0 Typ 3.3 3.3 2.5 3.3 240 10 55 175 Max 3.6 3.6 2.625 3.6 300 Units V V V V mA mA mA mA
LVCMOS/LVTTL Input Control Logic
VCCA = VCCD +3.3V 10%, VCCO = +2.5V 5% or +3.3V 10%; TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VCCA and VCCD are not internally connected. They must be connected together on the PCB. 6. ICC = ICCA + ICCO + ICCD.
Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
VIN = VCC VIN = 0.5V
-125 -300
150
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Reference Clock Input
VCCA = VCCD +3.3V 10%, VCCO = +2.5V 5% or +3.3V 10%; TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL VIN VDIFF-IN Parameter Input HIGH Voltage Input LOW Voltage Input Voltage Swing Differential Input Voltage Swing Condition RFCK, /RFCK RFCK, /RFCK RFCK, /RFCK, See Figure 1a. RFCK, /RFCK, See Figure 1b. -0.3 100 200 Min Typ Max VCCD + 0.3 Units V V mV mV
LVPECL Output DC Electrical Characteristics
VCCA = VCCD +3.3V 10%, VCCO = +2.5V 5% or +3.3V 10%, RL = 50 into VCCO-2V; TA = -40C to +85C, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF-OUT Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Swing Differential Output Voltage Swing See Figure 1a. See Figure 1b. Condition Min VCCO -1.075 VCCO -1.860 550 1100 800 1600 Typ Max VCCO -0.830 VCCO -1.570 Units V V mV mV
LVDS Output DC Electrical Characteristics
VCCA = VCCD +3.3V 10%, VCCO = +2.5V 5% or +3.3V 10%, RL = 100 across the pair; TA = -40C to +85C, unless otherwise stated.
Symbol VOUT VDIFF-OUT VOCM VOCM Parameter Output Voltage Swing Differential Output Voltage Swing Output Common Mode Voltage Change in Common Mode Voltage Condition See Figure 1a. See Figure 1b. Min 250 500 1.125 Typ 325 650 1.275 25 Max Units mV mV V mV
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AC Electrical Characteristics
VCCA = VCCD = +3.3V 10%; VCCO = +2.5V 5% or +3.3V 10%, RL (LVDS) = 100 across the output, RL (LVPECL) = 50 into VCCO-2V; TA = -40C to +85C, unless otherwise stated.
Symbol fIN fPHASE fOUT fVCO tSKEW tLOCK Parameter XTAL Input Frequency Range Reference Input Frequency Range Phase Detector Operating Frequency Range Output Frequency Range Internal VCO Frequency Range LVPECL Output Banks (0-3), Bank-to-Bank LVDS Output Banks (0-2), Bank-to-Bank Part-to-Part Skew PLL Lock Time Loop Filter Optimized for Cycle-to-Cycle Jitter * R = 130 * C1 = 0.47F * C2 = 100pF 1-Sigma Cycle-to-Cycle Jitter (XTAL Reference) 1-Sigma Cycle-to-Cycle Jitter (RFCK Reference) Deterministic Jitter Total Jitter Spur XTAL/RFCK Crosstalk-Induced Jitter PLL Bandwidth FOUT Duty Cycle Output Rise/Fall Time (20% to 80%) LVPECL Output Rise/Fall Time (20% to 80%) LVDS Condition Note 7 Min 14 14 14 73.5 2352 Typ Max 18 144 18 756 3024 50 50 200 10 Units MHz MHz MHz MHz MHz ps ps ps ms
Note 8 Note 9
15 15
tJITTER
Note 10 Note 10 Note 11 Note 12 Note 13 See "PLL Stability" Table
4 5 5.5 80 -35 28.8 43 100 80 8
6 7 8 100 0.7 99.8 57 400 300
psRMS psRMS psPP psPP
dBc@ fphase
BW tDC tr, tf
50 250 150
See "Synchronization" tPW_SYNC_MIN See "Synchronization" tPD_SYNC
Notes: 7. 8. 9. Fundamental mode, series resonant crystal.
8
psRMS kHz % ps ps Internal clock cycle Internal clock cycle
The bank-to-bank skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the same voltage and temperature. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
10. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 12. Total jitter definition: with an ideal clock input of frequency 12 23
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Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
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SY89537L Oscillator Tips 1. Mount the crystal as close to the SY89537L as possible to minimize parasitic effects. 2. Mount on the same plane as the SY89537 to minimize on via hole inductance. 3. To minimize noise pick up on the loop filter pins, cut the ground plane directly underneath the loop filter component pads and traces. 4. Keep the crystal and its traces away from adjacent noisy traces to minimize on noise coupling.
Table 4 illustrates the crystal specifications. Figure 2 below illustrates how to interface the crystal with the SY89537L.
Functional Description
Overall Function The SY89537L integrated programmable clock synthesizer and fanout buffer is part of a precision PLL-based clock generation family optimized for internal system clock generation for (FPGAs, ASICs, NPU) applications. Input MUX The device's input patent-pending MUX accepts both a single-ended or differential reference clock; and a 14MHz to 18MHz series resonant crystal (XTAL). The input MUX has built-in isolation, which minimizes crosstalk between the two inputs. The input MUX drives the PLLs phase detector, which expects a frequency between 14MHz and 18MHz, therefore, the reference clock can be a maximum frequency of 144MHz when the reference divider is set to: divideby-8. The minimum frequency that the reference accepts is 14MHz when the reference divider is set at: divide-by-1. PLL VCO The VCOs range of operation is from 2.352GHz to 3.024GHz, and the output frequency range is from 73.5MHz to 756MHz. The minimum output frequency is calculated according to the following equation:
fOUT = fphase x Pre Divider x FeedbackDi vider PreDivider x OutoutDivi der x PostDivide r
14MHz x 2 x 84 2x2x8
Figure 2. Crystal Interface
Quartz Crystal Selection: Note: Raltron Series Resonant: AS-16.666-S-SMD-T-MI (2) Raltron
fOUT (min) =
fOUT (min) = 73.5MHz The maximum output frequency according to the following equation:
fOUT (max) = 18MHz x 2 x 84 2 x 2 x1
is
calculated
External Loop Filter Considerations The SY89537L features an external PLL loop filter that allows the users to tailor the PLLs behavior. It is recommended that ceramic capacitors with NPO or X7R dielectric be used, since they have very low effective series resistance. For applications that require ultra-low, cycle-to-cycle jitter, use the components shown in Figure 3a. For best total jitter and best spur reduction, use the components shown in Figure 3b. Larger values of the pole capacitor (C2) results in less total jitter; however, the loop stability decreases. Loop stability decreases since the pole capacitor begins to dominate over the zero capacitor (C1). The external loop filter allows the user to change the loop filter values for specific jitter requirements. Using a smaller resistor in the loop filter decreases the PLLs loop bandwidth. This results in less noise from the PLL input, but potentially more noise from the VCO.
fOUT (max) = 756MHz
Crystal Input and Oscillator Interface The SY89537L features a fully integrated on-board oscillator, which minimizes system implementation cost. The oscillator is a series resonant, multi-vibrator type crystal driver.
Figure 3a. Loop Filter for Lowest Cycle-to-Cycle Jitter
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Figure 3b. Loop Filter for Lowest Total Jitter and Best Reference Spur Reduction
The reference spur is located at the phase detector frequency away from the carrier frequency. The attenuation of the reference spur is a function of the loop filter. Figure 4a shows the attenuation of the reference spur with the loop filter shown in Figure 3a. Figure 4b shows the attenuation of the reference spur with the loop filter shown in Figure 3b.
Figure 4b. Reference Spur at -52dB at 16MHz (R = 130, C1 = 0.47F, C2 = 1000pF)
Crystal Frequency: 14MHz to 18MHz
Mode of Oscillation: Fundamental
Min. Frequency Tolerance @25C Frequency Stability over 0*C to 70C Operating Temperature Range Storage Temperature Range Aging (per yr/1 3yrs) Equivalent Series Resistance (ESR) Drive Level 100
st
Power Supply Filtering Techniques
As with any high-speed integrated circuit, power supply filtering is very important. At a minimum, VCCA, VCCD, and all VCCO pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. To achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in Figure 5.
Typ. 30 50
Max. 50 100 +70 +125 5 50
Unit ppm ppm C C ppm W
-20 -55
Table 4. Quartz Crystal Oscillator Specifications Figure 5. SY89537L Recommended Power Supply De-Coupling
Note: For VCCA and VCCD use ferrite bead, Murata P/N BLM21A1025. For VCCO use ferrite bead, Murata, P/N BLM31P005.
Figure 4a. Reference Spur at -39dB at 16MHz (R = 130, C1 = 0.47F, C2 = 100pF)
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Synchronization
Output Synchronization Controlled by SYNC Timing Diagram
The SYNC control input is used to synchronize all divider outputs of the post divider. When a HIGH-LOW transition is applied to the SYNC control input the outputs are disabled when all post-divider outputs are LOW, see "Output Synchronization Controlled by SYNC Timing Diagram" for details. Once SYNC is
asserted with a rising edge, the outputs are enabled when all internal divider stages are reaching their LOW state. This ensures a simultaneous switching of all outputs with the next LOW-HIGH transition of the pre-divider clock.
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SY89537L loop stability in terms of damping factor, natural frequency, and bandwidth, and illustrates the pole and zero cutoff frequencies determined by the loop filter
PLL Stability For the loop filter configurations shown in Figure 3a and 3b, Table 5a and 5b below summarizes the PLLs
Parameter
VCC Temperature VCO Frequency Charge Pump Current Loop Filter Resistor Zero Capacitor Pole Capacitor VCO Gain (KVCO) Feedback Divider Phase Detector Frequency Damping Factor Natural Frequency Ratio=Phase Detector Freq/BW Zero Frequency Loop Bandwidth (BN) Pole Frequency 3 -40 2352 1.80E-04 130 4.70E-07 1.00E-09 3.20E+09 168 14 2.6 13600.29 197 2.61E+03 7.1E+04 1.22E+07 3 -40 2800 1.80E-04 130 4.70E-07 1.00E-09 4.50E+09 168 16 3.1 16127.95 160 2.61E+03 9.98E+04 1.22E+07 3 -40 3024 1.80E-04 130 4.70E-07 1.00E-09 4.50E+09 168 18 3.1 16127.95 180 2.61E+03 9.98+04 1.22E+07 3.3 25 2352 1.80E-04 130 4.70E-07 1.00E-09 2.80E+09 168 14 2.4 12721.90 225 2.61E+03 6.21E+04 1.22E+07 3.3 25 2800 1.80E-04 130 4.70E-07 1.00E-09 3.30E+09 168 16 2.6 13811.16 219 2.61E+03 7.32E+04 1.22E+07 3.3 25 3024 1.80E-04 130 4.70E-07 1.00E-09 3.10E+09 168 18 2.6 13386.09 262 2.61E+03 6.88E+04 1.22E+07 3.6 85 2352 1.80E-04 130 4.70E-07 1.00E-09 2.30E+09 168 14 2.2 11530.20 274 2.61E+03 5.1E+04 1.22E+07 3.6 85 2800 1.80E-04 130 4.70E-07 1.00E-09 1.70E+09 168 16 1.7 9912.83 424 2.61E+03 3.77E+04 1.22E+07 3.6 85 3024 1.80E-04 130 4.70E-07 1.00E-09 1.30E+09 168 18 1.9 8668.52 624 2.61E+03 2.88E+04 1.22E+07
Units
V C MHz A F F Hz/V Integer MHz
Hz
Hz Hz Hz
Table 5a. Optimized for Lowest Cycle-to-Cycle Jitter (R = 130, C1 = 0.47F, C2 = 100pF)
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Parameter
VCC Temperature VCO Frequency Charge Pump Current Loop Filter Resistor Zero Capacitor Pole Capacitor VCO Gain (KVCO) Feedback Divider Phase Detector Frequency Damping Factor Natural Frequency Ratio=Phase Detector Freq/BW Zero Frequency Loop Bandwidth (BN) Pole Frequency 3 -40 2352 1.80E-04 130 4.70E-07 1.00E-09 3.20E+09 168 14 2.6 13600.29 197 2.61E+03 7.1E+04 1.22E+06 3 -40 2800 1.80E-04 130 4.70E-07 1.00E-09 4.50E+09 168 16 3.1 16127.95 160 2.61E+03 9.98E+04 1.22E+06 3 -40 3024 1.80E-04 130 4.70E-07 1.00E-09 4.50E+09 168 18 3.1 16127.95 180 2.61E+03 9.98+04 1.22E+06 3.3 25 2352 1.80E-04 130 4.70E-07 1.00E-09 2.80E+09 168 14 2.4 12721.90 225 2.61E+03 6.21E+04 1.22E+06 3.3 25 2800 1.80E-04 130 4.70E-07 1.00E-09 3.30E+09 168 16 2.6 13811.16 219 2.61E+03 7.32E+04 1.22E+06 3.3 25 3024 1.80E-04 130 4.70E-07 1.00E-09 3.10E+09 168 18 2.6 13386.09 262 2.61E+03 6.88E+04 1.22E+06 3.6 85 2352 1.80E-04 130 4.70E-07 1.00E-09 2.30E+09 168 14 2.2 11530.20 274 2.61E+03 5.1E+04 1.22E+06 3.6 85 2800 1.80E-04 130 4.70E-07 1.00E-09 1.70E+09 168 16 1.7 9912.83 424 2.61E+03 3.77E+04 1.22E+06 3.6 85 3024 1.80E-04 130 4.70E-07 1.00E-09 1.30E+09 168 18 1.9 8668.52 624 2.61E+03 2.88E+04 1.22E+06
Units
V C MHz A F F Hz/V Integer MHz
Hz
Hz Hz Hz
Table 5b. Optimized for Total Jitter (R = 130, C1 = 0.47F, C2 = 1000pF)
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Micrel, Inc. Figure 6 shows the open and closed loop gain of the SY89537L. The closed loop-gain plot shows that the SY89537L when configured with the recommended loop filter values has essentially no jitter peaking near the -3dB point. In addition, the open loop curve shows the frequency at which unity gain occurs for a typical case of the SY89537L with VCC = 3.3V at TA = 25C. At unity gain, Figure 7 can be used to determine the phase margin or stability of the SY89537L.
SY89537L
Figure 8. VCO Frequency vs. Loop Filter Control Voltage at 3.3V, TA = 25C
dB
Frequency (Hz)
Figure 6. Open and Closed Loop Gain at VCC = 3.3V, TA = 25C
Figure 9. VCO Gain vs. Loop Filter Control Voltage at 3.3V, TA = 25C
Phase Margin ()
Input Interface
RFCK is designed to accept any differential or singleended input signal 300mV above VCC or 300mV below GND. RFCK should not be left floating. Tie either the true or complement input to GND, but not both. A logic zero is achieved by connecting the complement input to GND with the true input floating. For TTL input, tie a 2.5k resistor between the complement input and GND. LVDS, CML and HSTL differential signals may be connected directly to the reference inputs.
Frequency (Hz)
Figure 7. Phase Margin Plot at VCC = 3.3V, TA = 25C
Figure 8 illustrates the VCO frequency versus the loop filter control voltage at 3.3V, TA = 25C. The normal loop filter control voltage is -300mV to +300mV. Figure 9 illustrates the VCO gain curve at VCC = 3.3V, TA = 25C. With this set of information, determining the loop stability with other sets of loop filter configurations are possible.
Figure 10. Simplified Input Structure
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SY89537L
Input Termination
Figure 11a. LVPECL Interface (DC-Coupled)
Figure 11b. LVPECL Interface (AC-Coupled)
Figure 11c. CML Interface (DC-Coupled)
Figure 11d. CML Interface (AC-Coupled)
Figure 11e. LVDS (DC-Coupled)
Figure 11f. 2.5V LVPECL (DC-Coupled)
Figure 11g. 2.5V CML (DC-Coupled)
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SY89537L
Output Bank and Frequency Control
There are five independently programmable output frequency banks, four differential LVPECL output banks and one differential LVDS output bank with three output pairs. Each bank has frequency control SELx and Enx to generate different divider ratios (see "PECL and LVDS Output and Frequency Select" Tables). It can be programmed for pass-through, internal divided VCO clock divide-by- /2, /8 or disable state. When disabled, the non-inverted output goes to static LOW and the inverted output goes to static HIGH.
Output Logic Characteristics See "Output Termination Recommendations" for proper termination. When LVPECL single-ended output is desired, the unused complimentary output should be terminated. Unused LVPECL output pairs can be left floating. LVDS output pairs should be terminated with 100 across the pair. In order to minimize jitter and skew, unused LVDS output banks and unused LVDS output pairs should be terminated with 100 across each pair. LVPECL Outputs:
* * * * Typical voltage swing is 800mV into 50. Common mode voltage is VCCO-1.3V. Typical voltage swing is 325mV into 100. Common mode voltage is 1.2V.
Figure 12a. Parallel Thevenin-Equivalent
Figure 12b. Parallel Termination
LVDS Outputs:
Output Termination Recommendations
LVPECL LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing which results in low EMI. LVPECL is ideal for driving 50-and-100-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel Termination TheveninEquivalent, Parallel Termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.
LVDS LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.
Figure 13a. LVDS Differential Measurement
Figure 13b. LVDS Common Mode Measurement
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Micrel, Inc.
SY89537L
Related Product and Support Documentation
Part Number SY89538L Function 3.3V, Precision LVPECL and LVDS Programmable, Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay New Products and Applications MLF
TM
Data Sheet Link http://www.micrel.com/product-info/products/sy89538l.shtml
HBW Solutions
www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf
Application Note
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Micrel, Inc.
SY89537L
Package Information
44-Pin MLFTM (MLF-44)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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